`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:38:52 05/05/2013
// Design Name:   instr_decoder
// Module Name:   C:/Users/btgarber/Documents/College/CSE 320 - Spring 2013/Lab3/tb/tb_instr_decoder.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: instr_decoder
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_instr_decoder;

	// Inputs
	reg [7:0] instr_data;
	reg clk;
	reg reset;
	reg instr_exec;

	// Outputs
	wire [3:0] o_data;
	wire [1:0] o_addr;
	wire LDR;
	wire SUM;
	wire CMP;
	wire MUL;
	wire alu_en;

	// Instantiate the Unit Under Test (UUT)
	instr_decoder uut (
		.instr_data(instr_data), 
		.clk(clk), 
		.reset(reset), 
		.instr_exec(instr_exec), 
		.o_data(o_data), 
		.o_addr(o_addr), 
		.LDR(LDR), 
		.SUM(SUM), 
		.CMP(CMP), 
		.MUL(MUL), 
		.alu_en(alu_en)
	);

	initial begin
		// Initialize Inputs
		instr_data = 0;
		clk = 0;
		reset = 0;
		instr_exec = 0;
		#5
		forever #5 clk <= ~clk;
	end
	
	initial begin
		@(posedge clk) reset=1;
		@(posedge clk) instr_data=8'b0000_0001;	instr_exec=0; // LDR into A
		@(posedge clk) instr_exec=1;									  // Execute the operation
		@(posedge clk) instr_data=8'b0001_0010;	instr_exec=0; // LDR into B
		@(posedge clk) instr_exec=1;									  // Execute the operation
		@(posedge clk) instr_data=8'b0110_0100;	instr_exec=0; // SUM into C from A and B
		@(posedge clk) instr_exec=1;									  // Execute the operation
		@(posedge clk) instr_data=8'b1011_0100;	instr_exec=0; // MUL into D from A and B
		@(posedge clk) instr_exec=1;									  // Execute the operation
		@(posedge clk) instr_data=8'b1111_0100;	instr_exec=0; // CMP into D from A and B
		@(posedge clk) instr_exec=1;									  // Execute the operation
		@(posedge clk) instr_exec=0;									  // END
	end
      
      
endmodule

